1. Field of the Invention
The invention relates to a semiconductor memory device technique of a dynamic random access memory (DRAM). More particularly, the invention relates to a semiconductor memory device technique of performing a refresh operation to memory cells of specified word line address intervals, so as to reduce power consumption.
2. Description of Related Art
In a dynamic random access memory (DRAM), an amount of charges stored in a capacitor is used to represent “1” or “0” of a binary bit, so that each memory cell of the DRAM only requires one capacitor and one switch (or one transistor).
During an actual operation, the capacitors in the DRAM may have an electric leakage phenomenon, which may cause an insufficient potential difference of the capacitors, so that data stored in the DRAM can be disappeared. Therefore, the DRAM has to enter a refresh mode to periodically refresh (which can also be referred to as data charging/data refreshing) all of the memory cells, so as to ensure correctness of information stored in the DRAM. As shown in FIG. 1 and FIG. 2, FIG. 1 is a block diagram illustrating a conventional DRAM unit 10, and FIG. 2 is a signal waveform diagram of a data refreshing method of the conventional DRAM unit 10. Referring to FIG. 1, the DRAM unit 10 includes a memory array 110, a refresh timing controller 120 and a word line address counter 130. The memory array 110 includes a plurality of word lines and a plurality of bit lines. The word lines are perpendicularly intersected to the bit lines, and each intersection thereof has a memory cell for storing a binary (i.e. “0” or “1”) bit information.
The refresh timing controller 120 receives an entry refresh signal Sref, so as to determine whether the DRAM unit 10 is in the refresh mode. During the refresh mode, the refresh timing controller 120 generates a refresh clock signal Sclk (referring to FIG. 2), and the word line address counter 130 cyclically calculates a word line address WL according to the refresh clock signal Sclk. In the present embodiment, each pulse interval of the refresh clock signal Sclk is 8 μS, so as to avoid excessive long refresh period that causes an error of data stored in the memory array 110. Moreover, the word line address WL of the memory array 110 is composed of hexadecimal number of three digits, and a word line addresses interval of the memory array 110 is between 000H and FFFH, so that after the word line address counter 130 sequentially counts from 000H to FFFH, the word line address counter 130 restarts the counting from 000H. The memory array 110 continually receives the refresh clock signal Sclk and the word line address WL during the refresh mode, so as to periodically refresh all of the memory cells in the memory array 110. However, during an application of the DRAM, not all of the memory cells are stored with data, so that when the memory cells that are not stored with data are charged/refreshed, extra charges are consumed.
Therefore, multiple DRAM refreshing techniques are developed to reduce the power consumption of the DRAM in the refresh mode. U.S. Pat. No. 6,590,822 discloses a self-refresh memory device, and in such memory device, a refresh command signal generated by a computer system is used to mask one or a plurality of bits in a word line address data, and a part of (for example, ½, ¼, ⅛ or 1/16, etc.) RAM memory blocks are provided in advance for data storage and the refresh operation, and other memory blocks are disabled, so as to reduce the power consumption. However, only a fixed rate (for example, ½, ¼ or ⅛, etc.) of the memory capacity of the above memory device can be used to store data. In case of an excessively large memory capacity, extra power is consumed for the memory blocks that are not stored with data during the data refreshing operation, and in case of an excessively small memory capacity, the memory device is not applicable for the computer system. Regarding the above memory device, the computer system cannot specify the required memory capacity in detail, so that a degree of freedom of the DRAM used by the computer system is reduced.